SSL 1600 yuSynth Triple Clock Divider (Dotcom/5U)
The three dividers can be clocked by the same clock signal on input IN #1, but a different master clock can be used for the second and third dividers by plugging it in the input IN #2 & 3.
The divided clock signals are available at outputs OUT #1, OUT #2 and OUT #3, and are visualized with LEDs.
A RESET input is provided to synchronize the dividers. Note that the outputs are all shaped to the same pulse width as that of the external clock.
Example : one master clock, STEP #1 = 1/2, STEP #2 = 1/3, SETP #3 = 1/5